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Speeding up emulation-based diagnosis techniques for logic cores
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Speeding up emulation-based diagnosis techniques for logic cores

Shyue-Kung Lu, Yin-Mou Chen, Shi-Yu Huang 和 Cheng-Wen Wu
IEEE Design and Test of Computers, 卷.28(4), 頁碼.88-97
07/2011
DOI: https://doi.org/10.1109/MDT.2011.25

摘要

circuit partitioning design and test fault emulation fault injection fault-injection scan chain logic diagnosis Hardware and Architecture Software Electrical and Electronic Engineering
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system. © 2011 IEEE.

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