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Statistical modeling for postcycling data retention of split-gate flash memories
Journal article   Peer reviewed

Statistical modeling for postcycling data retention of split-gate flash memories

Ling-Chang Hu, An-Chi Kang, J.R. Shih, Yao-Feng Lin, Kenneth Wu and Ya-Chin King
IEEE Transactions on Device and Materials Reliability, Vol.6(1), pp.60-65
03/2006

Abstract

Lifetime model Low-temperature data retention (LTDR) Program/erase (P/E) cycling Reliability Split-gate Flash memory Stress-induced leakage current
In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling. © 2006 IEEE.

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