摘要
The characteristics of thermal conductivity with different operated temperatures , material thicknesses , and impurity concentrations are studied by thermoelectric measurements and developed simulation model for the study of self-heating effect. With the input of these module-level material properties in our developed finite-element model, the self-heating effect on the CMOS logic transistors from 20-to 5-nm technology nodes are investigated systematically and accurately. The maximum chip temperature in the 14/16-nm technology node Si FinFET device is 170 °C. On the other hand, the higher operated temperature is also observed in high mobility material devices such as Ge and III-V (InAs) FinFETs due to their poor material properties of -value. It indicates that these high mobility materials are hard to be used in the next generation scaled technology node devices, unless these devices can be operated at the ultralow voltage bias (<0.5 V for InAs and <0.8 V for Ge) from the self-heating effect point of view.