Abstract
A parallel-in-parallel-out systolic array and a serial-in-serial-out systolic array are proposed for fast multiplication in finite fields GF(2m) with the standard basis representation. Both of the architectures possess features of regularity, modularity, concurrency, and unidirectional data flow. As a consequence, they have high throughput rates and are well suited to VLSI implementation with fault-tolerant design. As compared to the related multipliers presented by Yeh et al., the proposed parallel implementation is easier to incorporate fault-tolerant design and the proposed serial implementation requires only one control signal, instead of two. © 1991 IEEE