Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

Shih-Chieh Chang; Malgorzata Marek-Sadowska; TingTing Hwang

doi:10.1109/43.541442

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Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

Journal article

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Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

Shih-Chieh Chang, Malgorzata Marek-Sadowska and TingTing Hwang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.15(10), pp.1226-1236

1996

DOI: https://doi.org/10.1109/43.541442

Abstract

This paper proposes an efficient algorithm for technology mapping targeting table look-up (TLU) blocks. It is capable of minimizing either the number of TLU's used or the depth of the produced circuit. Our approach consists of two steps. First a network of super nodes, is created. Next a Boolean function of each super node with an appropriate don't care set is decomposed into a network of TLU's. To minimize the circuit's depth, several rules are applied on the critical portion of the mapped circuit. © 1996 IEEE.

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Title: Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams
Creators - without role: Shih-Chieh Chang - National Chung Cheng University
Malgorzata Marek-Sadowska - National Chung Cheng University
TingTing Hwang - National Tsing Hua University
Publication Details: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.15(10), pp.1226-1236
Identifiers: 9957766585106774
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Journal article

Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

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