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Temporal logic replication for dynamically reconfigurable FPGA partitioning
Journal article   Peer reviewed

Temporal logic replication for dynamically reconfigurable FPGA partitioning

Wai-Kei Mak and Evangeline F.Y. Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.22(7), pp.952-959
07/2003

Abstract

Dynamically reconfigurable FPGAs Field-programmable gate arrays Logic replication Reconfigurable computing Temporal partitioning
In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. Given a K-stage temporal partition, the min-area min-cut replication problem is defined and we present an optimal algorithm to solve it. We also present a flow-based replication heuristic which is applicable when there is a tight area bound that limits the amount of possible replication. In addition, we show a correct network flow model for partitioning sequential circuits temporally and propose a new hierarchical How-based performance-driven partitioner for computing initial partitions without replication.

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