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Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package
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Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng 和 Min-Jer Wang
IEEE Design and Test, 卷.34(3), 頁碼.50-58
06/2017
DOI: https://doi.org/10.1109/MDAT.2016.2562060

摘要

3D IC cost model InFO WLCSP test cost analysis wafer probe wafer test Software Hardware and Architecture Electrical and Electronic Engineering
To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure. - Jin-Fu Li, National Central University.

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