摘要
The self-heating effect on Si <sub>1-x</sub> Ge <sub>x</sub> based FinFETs is analyzed and investigated with different device structures/dimensions, Ge concentration, and operated voltages. The module-level material properties of the thermal conductivities (k) in Si and Ge with different operated temperature (T), material thickness (t), and impurity concentration (N) are calibrated by the experimental thermo-electric measurement firstly in our simulation model. The maximum chip temperature in the Ge FinFETs is found to be ∼50 °C higher than in the Si FinFETs due to the poor intrinsic material property of k in Ge material. This seriously limits the development of the Ge FinFETs in the future scaled logic devices even Si <sub>1-x</sub> Ge <sub>x</sub> material (x>0.8) has the higher intrinsic carrier mobility than pure Si. One of the possible solutions to avoid this self-heating effect in Si <sub>1-x</sub> Ge <sub>x</sub> based FinFETs is to reduce the operated voltage (<0.8V) to get the optimal device operated window among different boundary conditions including the acceptable chip temperature and the higher carrier mobility in the device.