摘要
This paper investigates the origin of NAND cell degradation during the time interval (t wait ) between program/erase (P/E) cycles. It is observed that, at room temperature, the transconductance reduction (DG m ,max ) is sensitive to t wait from erase-to-program, and longer t wait from erase-to-program results in larger DG m ,max. In contrast, DG m ,max has almost no clear dependence on t wait from program-to-erase. Using our previous statistical DG m ,max method, the activation energy (E A ,G ) of oxide damage creation is extracted. As the starting voltage (V CG ,0 ) of incremental step pulse programming (ISPP) varied from 14.6 to 17.6 V, E A ,G has a shift of about 11 meV and 13 meV for both t wait from erase-to-program of 0.1 s and 4 s, respectively. We also found that E A ,G linearly decreases as the maximum oxide field increases during ISPP. It would be plausible to consider a model in which the program steps generated holes inside the tunneling oxide, which recombined with inversion electrons near Si/SiO 2 interface during t wait from erase-to-program. This process generates more trap states and thus results in larger DG m ,max.