摘要
As semiconductor devices are increasingly employed in consumer electronics and industrial applications, cycle time reduction is critical for semiconductor companies to maintain competitive advantages. Semiconductor manufacturing is capital intensive, in which fab capacity is configured by the interchangeable tools that can be allocated for different steps of reentrant processing. Focusing on realistic needs, this study aims to propose a novel approach that integrates data mining approach to forecast arrival rates and determining the allocation of interchangeable tool sets to reduce the work in process (WIP) bubbles for cycle time reduction. In particular, a hybrid approach of decision tree and back-propagation neural network (BPNN) was developed to forecast the arrival rates of individual tool sets and thus predict the WIP levels of individual tool sets. Therefore, the tool allocation decisions can be generated to minimize the total WIP of interchangeable tool sets given the same throughput level. An empirical study was conducted in a leading semiconductor company in Taiwan for validation. The results have shown practical viability of the proposed approach that can effectively reduce WIP and increase capacity utilization in real settings.