摘要
We investigate endurance degradation in hafnium oxide ( HfO2 )-based ferroelectric field effect transistors (FeFETs) by analyzing interface ( N-it ) and near-interface oxide traps ( N-ox ) using a two-level charge pumping (CP) technique. After 104 program (PG) / erase (ER) cycles at +/- 5 V, 100ns, Nit increases by similar to 2x , and the memory window (MW) reduces from 1.2V to 0.45V. Temperature-dependent measurements reveal accelerated trap generation above 50 degrees C, with decreasing charge-pumping current ( I-CP(max) ) due to deeper oxide trap occupation. Pulse parameter tuning shows that longer rise/fall times, and shorter hold durations mitigate Nit accumulation and delay memory window collapse. The extracted average interface trap density ( D-it ) reaches similar to 4x10(12) cm(2)eV(1) after cycling. These results emphasize the role of trap engineering in improving FeFET endurance for scaled non-volatile memory applications.