摘要
This work reviews the fundamentals of the Mueller-Muller Phase Detector (MMPD) and explores its application in multilevel signaling. We analyze and highlight the advantages of adopting inner data levels for error sampling. To mitigate the worsened ISI-induced jitter in multilevel signaling, this work further proposes an unbalanced MMPD operation that improves the phase detection confidence, easing the trade-off between dithering jitter and tracking ability. Our results demonstrate that the unbalanced MMPD design effectively enhances PD gain, making it a promising solution for high-speed wireline transceivers. The unbalanced MMPD is integrated into the CDR circuit of an 80-Gb/s PAM6 receiver for verification. The receiver features a 3-bit SAR ADC with uneven slicing levels. Utilizing LSB conversion for error sampling, this ADC achieves data and error sampling without additional error samplers. Measurement results from a 28-nm CMOS prototype demonstrate higher tracking bandwidth with an eye-opening margin of over 176 mUI. At 80 Gb/s, the receiver consumes 166.5 mW with an energy efficiency of 2.08 pJ/bit.