Unified VLSI systolic array design for LZ data compression

Shih-Arn Hwang; Cheng-Wen Wu

doi:10.1109/92.931226

Unified VLSI systolic array design for LZ data compression

期刊文章

同儕審查

Unified VLSI systolic array design for LZ data compression

Shih-Arn Hwang 和 Cheng-Wen Wu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷.9(4), 頁碼.489-499

08/2001

DOI: https://doi.org/10.1109/92.931226

摘要

CAM

Data compression

LZ77

LZ78

LZSS

LZW

String matching

Systolic array

Software

Hardware and Architecture

Electrical and Electronic Engineering

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup.

指標

1 檢視次數

詳細資料

題名: Unified VLSI systolic array design for LZ data compression
翻譯題名: Unified VLSI systolic array design for LZ data compression
創作者：: Shih-Arn Hwang (作者) - National Tsing Hua University
Cheng-Wen Wu (作者) - IEEE
學術資源類型: 期刊文章
出版日期: 08/2001
出版資訊: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷.9(4), 頁碼.489-499
語言: 英語

Unified VLSI systolic array design for LZ data compression

摘要

相關連結

指標

詳細資料

National Tsing Hua University 社交媒體