摘要
In this work, p-channel MOSFETs with the metal-gate electrode and high-k gate stack of ZrO 2 /Al 2 O 3 /GeO 2 on n-Ge substrate are fabricated and investigated. The interface state generation (ΔN it ) and hole trapping (ΔN ot ) during voltage stresses are examined. According to the time dependence on the subthreshold swing and the threshold voltage, both ΔN it and ΔN ot can be extracted during the gate voltage stresses, which is characterized by the power-low (t n ) model. The time exponent of ΔN it is in the range of 0.48-0.65 which is approximately two times that of ΔN ot . Based on the Si/oxide model, the charged H + diffusion may be the dominant process in the degradation of interface states. In the early stressing, the device degradation of threshold voltage shift mainly results from the hole trapping in the gate dielectrics. However, the long-term trend indicates that ΔN ot will be overwhelmed by ΔN it after a characteristic time (t c ). This implies, for the device degradation during gate voltage stresses, the contribution of ΔN ot decreases with time, meanwhile, the contribution of ΔN it increases with time. According to the experimental results, the characteristic time is approximately independent of stress voltage and is about 10 6 s.