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Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies
Journal article   Peer reviewed

Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies

Yi-Pei Tsai, Chun-Hsiung Wu, Chrong Jung Lin and Ya-Chin King
IEEE Transactions on Electron Devices, Vol.63(6), pp.2497-2502
01/06/2016

Abstract

Advanced fin-shaped field effect transistors (FinFET) technology plasma-induced damage (PID) slot contact.
We propose a novel approach for monitoring the wafer-level plasma-induced charging effect in advanced CMOS fin-shaped field effect transistor (FinFET) processes, and successfully demonstrate that ON-chip charge collectors, consisting of antenna-coupled floating gates (FGs), can record the plasma charging levels during back-end-of-the-line processes. The charge stored on these in situ recorders helps to project the actual potential on the transistor gates during plasma-charging stress. Wafer maps containing the potential distribution, as estimated by the level of positive and negative charging effects on the FGs, provide a powerful tool for future FinFET process optimization and yield additional insights for device reliability analysis.

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