Abstract
It is known that by extracting log-likelihood ratio (LLR) values from the received MIMO signals, a MIMO detector is able to exchange a posteriori soft information with a channel decoder to improve the error performance. A minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is considered to be a practical MIMO detector, but the computational complexity for the LLR computation is still at a high level for higher-order modulations. This paper presents a low-complexity LLR computation algorithm together with the hardware implementation for MMSE-PIC detectors. The complexity is evaluated using logic synthesis based on a 90-nm CMOS technology. For 256-QAM modulation, a 50% reduction in area is achieved. In addition, a 44% reduction in area can be achieved for a multi-mode MMSE-PIC detector that supports multiple modulations for signals up to 256-QAM.