Abstract
A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically decide the maximum operating frequency of the CUT. The search process for this maximum operating frequency is conducted by a binary search in which the next frequency to test CUT is determined automatically by the BISG controller based on whether the CUT passes or fails the BIST session at current frequency. The maximum operating frequency the CUT can operate is narrowed down to a fine-tuning range out of a number of clock frequencies that the ADPLL can offer. The frequencies an ADPLL can offer is divided into a plurality of coarse ranges, with each of them further having a plurality of fine-tuning frequencies. In this overall built-in speed grading process, each desired frequency to be used to test the CUT is generated by the ADPLL via a binary-neighborhood-linear locking scheme, so as to minimize the locking error between the desired frequency and the frequency actually produced by the ADPLL even under process variation. In this process, a desired clock frequency for a BIST session is locked in by the ADPLL in three steps: a quick binary search to find a coarse range of frequencies close to the desired frequency; a neighborhood checking around the selected coarse range in an attempt to find one that is even closer to the desired frequency; and finally an exhaustive or linear search within the final selected coarse range for a fine-tuning frequency that is closest to the desired frequency. Such a process provides better immunity to potential process variation under advanced technologies.