Circuit Re-Synthesis And Method For Delay Variation Tolerance

National Tsing Hua University; 張世杰

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Circuit Re-Synthesis And Method For Delay Variation Tolerance

National Tsing Hua University and 張世杰

22/06/2006

Abstract

By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.

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Title: Circuit Re-Synthesis And Method For Delay Variation Tolerance
Creators - without role: National Tsing Hua University
張世杰
Identifiers: 9957787930106774
Note: 優先權US 20040014170 20041217
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Patent
Patent: US 7,224,178 B2; US 7,224,178 B2
Date application: 17/12/2004

Circuit Re-Synthesis And Method For Delay Variation Tolerance

Abstract

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