Abstract
Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.