Abstract
A high-speed built-in self-test (BIST) circuit for dynamic random access memory (DRAM) is disclosed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The circuit includes two finite state machines, instead of the conventional single finite state machine. Therefore, a pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design. In addition to pipelining, protocol-based relaxation is also presented. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design.