Abstract
The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.