Abstract
A liquid crystal display device has a pair of substrates at least one of which is transparent, a liquid crystal layer sandwiched by the pair of substrates, a video signal line, a drain electrode, a pixel electrode which receives a video signal from the video signal line through the drain electrode and a thin-film transistor, a gate electrode for turning the thin-film transistor on, a counter electrode to which a counter voltage is applied through a counter voltage signal line, and a storage capacitor formed by superposing part of said pixel electrode on part of said counter voltage signal line via an interlayer insulating film. In the liquid display device are formed pixels where the light transmission factor of the liquid crystal is changed by use of an electric field which is established between the pixel electrode and the counter electrode and has the component in parallel with the surface of the substrate, the dielectric constant anisotropy .DELTA..epsilon., the effective thickness deff of the liquid crystal layer, the width Wp of the pixel electrode in the short-side direction, the width Wc of the counter electrode in the short-side direction, and the gap L between the pixel electrode and the counter electrode satisfy the following relationships, .DELTA..epsilon.>0, 2.8 .mu.m.ltoreq.deff.ltoreq.4.5 .mu.m, and 1.2.times.deff.ltoreq.Wp.ltoreq.L/1.2, 1.2.times.deff.ltoreq.Wc.ltoreq.L/1.2, or .DELTA..epsilon.<0, 4.2 .mu.m.ltoreq.deff.ltoreq.8.0 .mu.m, and 1.2.times.deff.ltoreq.Wp.ltoreq.L/1.2, 1.2.times.deff.ltoreq.Wc.ltoreq.L/1.2. When the scanning signal lines connected to the gate electrodes and the counter voltage signal lines connected to the counter electrodes are arranged in parallel in the direction of row of a plurality of pixels arranged in the form of a matrix and when the video signal lines connected to the drain electrodes are arranged in parallel in the direction of column, the counter voltage signal line is used in common by the two pixels adjacent to each other in the direction of column. Alternatively, both ends of the counter voltage signal lines are connected to the common bus line and are further connected to the counter electrode driver means.