Abstract
A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets.