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MOS type semiconductor device
Patent

MOS type semiconductor device

白田理一郎 and Seiichi Aritome
20/02/1990

Abstract

A MOS type semiconductor device includes two adjacent MOSFETS. The FETS are respectively formed on element forming areas of a P-type substrate. Each of the transistors has N+ type layers serving as the source and drain thereof they have a common gate electrode layer. Each of the FETS has a contact hole formed in one of the N+ type layers. A wiring layer is to be connected to the contact hole. A P+ type heavily doped semiconductor layer substantially intersects the common gate electrode layer between the FETS in the substrate. The layer functions as an inversion prevention layer. The inversion prevention layer projects from the common gate electrode layer towards the contact hole. The common gate electrode layer has a concave portion in an area of intersection with the inversion prevention layer, whereby an effective projection distance of the inversion prevention layer is increased while an opposition distance between the front edge of the inversion prevention layer and the contact hole section is kept from being set to be less than a previously required value.

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