Abstract
A method for verifying a circuit design includes a step of assigning numerical values 1/a.sub.i to input ports of the circuit design according to a function a.sub.i+1=(a.sub.i-1).sup.2+1, wherein i represents the number of the input port and the numerical value a.sub.1 is not equal to 2 or 1. Preferably, a.sub.1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l's probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.