Abstract
The present invention discloses a built-in self-test (BIST) circuit for RAMBUS DRAM. Unlike other usual memory devices, RAMBUS DRAM can perform its input stimuli in accordance with a complicated protocol at an extremely high operation speed (400 MHz). In order to perform a high-speed test, a new BIST structure is therefore required. The BIST structure consists of three key elements, including two interactive finite state machines and a high-speed time division multiplexer. The two finite state machines together define the potential test algorithm and generate the sequential memory commands. By means of the time division multiplexer, each memory command can further correspond to a multi-cycle package ideal for RAMBUS DRAM. Among these elements, the finite state machines often encounter operation bottlenecks. A simple master-slave synchronous mechanism may be applied to convert the two finite state machines into a multi-cycle path element as a solution for the time restriction.