Abstract
A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the ONO sidewall.