The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.
- Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized
- National Tsing Hua University黃稚存YEN JU HOMING CHANG HSIEH
- 9957787742106774
- 優先權US 20080138226 20080612
- Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
- Traditional Chinese
- Patent
- US 7,861,070 B2; US 7,861,070 B2
- 11/06/2008