Abstract
A memory device including a gate electrode, a charge trapping layer, a gate dielectric layer, a polysilicon layer, and twodrain/source regions is provided. The charge trapping layer is located under the gate electrode. The oxide layer is located under the trapping layer. The polysilicon layer is located under the oxide layer and over a glass substrate. The two drain/source regions are formed in the polysilicon layer and are located on the two sides of the gate electrode. A tunable current driver and an operating method thereof are also disclosed in specification.