Abstract
A new moment computation technique for general lumped circuits with resistor loops in high-speed VLSI circuits design is proposed. In the invention, the signal delay of circuits including resistors, capacitors, inductors and conductors can be calculated using the concept of tearing. A lumped network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. Using the superposition theorem and substitution theorem, the moment can be updated by adding the links back to the original circuits. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments of circuits with resistor loops efficiently.