Abstract
A method and apparatus for model-order reduction of general RLC interconnects in high-speed VLSI is disclosed. It has been known that reduced-order models can be yielded using the congruence transformation, which contains information of circuit moments of both circuit network and its corresponding adjoint network. By exploring symmetric properties of the modified nodal analysis formulation, the method needs only half of the system moment information compared with the previous ones. Passivity of the reduced-order model is still preserved.