Abstract
The present invention discloses a differential sensing and TSV timing control scheme for 3D-IC includes a first chip layer of the stacked device including a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal conductive line, a first differential signal driver is coupled the sensing circuit, horizontally. A Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer; wherein the N is a nature number and is more than one; wherein the Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N-2) relative high loading TSVs to act dummy loadings, the relative low loading TSV and (N-2) relative high loading TSVs penetrating the stacked device from the Nth chip layer to the first chip layer, wherein the relative low loading TSV and the (N-2) relative high loading TSVs are formed in a shared configuration; wherein the Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of relative low loading TSVs and (N-2) pairs of relative high loading TSVs, vertically, the pair of relative low loading TSVs and the (N-2) relative high loading TSVs penetrating the stacked device from the Nth chip layer to the first chip layer; and each the relative low loading TSV being formed between a first and a second chip layers, each the relative high loading TSV being formed between any adjacent two chip layers of the stacked device.