Abstract
A three dimensional chip detector in each layer of a stack assembly comprises: a surge generator, which can receive an initial signal and generate a surge input signal to the detector on the next layer; a latch, which is coupled with the surge generator so as to receive the output signal of the surge generator and generate a layer identification signal; a counter, which is coupled with the detector on the previous layer and the initial signal so as to execute a counting operation; an adder, which is coupled with the counter so as to add a numerical value to the counter so that an output and input increase signal is counted to the surge generator.