Abstract
This invention relates to a power estimation method using chip design register transmission layer. It comprises the following procedures: (A) it analyzes all possible branches of the conditional statement in the description language transmitted by a register, and sets up power models corresponding to each possible conditional branch; (B) it selects plural representative input vector sets from the input vector that sets recorded by the chip specification. According to the selected input vector set, it sets up linear characteristic equations corresponding to each power model; (C) it enters each input vector set recorded in the chip specification into a corresponding liner characteristic equation to calculate a power value. Eventually, it obtains an average power consumption representing the chip power consumption from all calculated power values.