Abstract
The present invention provides a low-complexity and multi-mode Low-Density Parity-Check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified architecture is implemented so that the hardware resources can be reused in different modes. In addition, memory accesses are achieved via routing networks with fixed interconnections and memory address generators, accordingly reducing the complexity of the hardware implementation. Further, the present invention provides an early termination with which the iterative operations can be terminated when a threshold is reached so that the power consumption can be thus reduced. The early termination shares a part of the hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.