Abstract
This invention provides a compiler framework for employing power-gating mechanism to reduce leakage power dissipation. With a program as the input, this approach comprises: to construct the control-flow graph of the program; to estimate the component activities on a microprocessor within the program; to generate a first power-gating instruction scheduling to determine when, where, and whether power-gating control should be employed with the concern of power reduction; to generate a second power-gating instruction scheduling with a Sink-N-Hoist framework to merge several power-gating instructions as one compound power-gating instruction; to insert the power-gating instruction into the program according to the second power-gating instruction scheduling.