Abstract
A flash memory manufacturing method employing the CMP to planarize the floating gate is disclosed. First, a LOCOS of STI method is used to form the isolation area and then form a thin tunneling oxide layer. Second, a floating gate is deposited on the tunneling oxide layer, and then the floating gate is planarized via the CMP method and each of the floating gates is defined, or the floating gate is directly planarized via the CMP method and the isolation layers are exposed beside the floating gate. Then oxide/nitride/oxide insulated layers are formed and then doped poly silicon and tungsten silicide control gate are formed. Third, a single memory cell is formed and the source/drain is made via an ion implantation to finish the flash memory process.