Abstract
A 3D electronic packaging structure is provided in this invention. The first electronic device is attached to the second one where the devices toward outward, and then they are embedded in a chip carrier. There are conductive vias in the chip carrier. After connecting the first and the second electronic device to the chip carrier, the vertical interconnections are constructed to make a 3D electronic packaging structure. Moreover, there are no vias in the electronic device which prevents the device from failure in the via-manufacturing processes. Furthermore, the attached chips reduce the packaging height because the junction layers are decreased.