Abstract
A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The PMA clock tree includes a sub-clock-tree and a PMA buffer. The sub-clock-tree transmits a delayed clock signal to a function module. A power mode of the function module is decided by power information. The PMA buffer couples to the sub-clock-tree. The PMA buffer decides delay time of a system clock signal according to the power information, and outputs the delayed system clock signal as the delayed clock signal to the sub-clock-tree.