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去除靜態隨機存取記憶體漏電流影響之電路及方法
Patent

去除靜態隨機存取記憶體漏電流影響之電路及方法

國立清華大學, 黃錫瑜 and 賴亞群
01/08/2008

Abstract

An apparatus for removing impact of leakage current in SRAM comprises a bit-line pair including a first bit-line and a second bit-line, a pre-charge circuit connected to the bit-line pair for charging the bit-line pair, a plurality of memory cells connected between the first and second bit-lines, a sense amplifier for detecting voltage difference of the bit-line pair, and a calibration circuit connected between the memory cells and the sense amplifier. Through the calibration circuit, a voltage at the first bit-line, in which leakage current may occur, is transmitted to the calibrated second bit-line between the calibration circuit and the sense amplifier, a voltage at the second bit-line is transmitted to the calibrated first bit-line between the calibration circuit and the sense amplifier, and those voltages are reflected on the input signals of the sense amplifier, so as to remove the impact of leakage current.
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