Abstract
The present invention relates to a flash memory cell array structure, in which each memory cell includes a split-gate memory cell and a selected transistor. A source/drain of the selected transistor is serially connected with the source of the split-gate memory cell; the other source/drain of the selected transistor is connected with the selected transistor of another memory cell. In other words, two neighboring rows are mirror-symmetrical, and each word line are connected with the respective control gate of each row of flash memory cells; moreover, each transmission gate lines are also connected with the respective gate of all selected transistors; each source line is connected with the connection terminals of all two neighboring selected transistors of eight neighboring bit lines. Besides, each bit line is connected with the drain of each split-gate memory cell respectively on the same row. The structure of the present invention won't interfere with the memory cells of neighboring columns while programming a column of memory cells, and the memory cell of each byte associated with each cell on the same column can be either individually erased by data or not be erased.