Abstract
A method of multi-port memory test is disclosed. The multi-port memory has plural accessing ports to access all memory cells (memory addresses) in parallel, and the test method comprises providing at least a test unit including at least a test operation, and proceeding the test operation included sequentially to each memory cell (memory address) through the accessing ports. Especially, the test method is to dispatch the test operations to the accessing ports when the test unit comprises plural test operations, and to proceed the dispatched test operation to the same memory cell by the accessing ports during the clock period of testing the memory cell (memory address), so that the test time of multi-port memory is effectively shortened.