Abstract
The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.