Abstract
A LDPC code layered decoding architecture with reduced number of hardware buffers decodes by storing a variable-to-check message. When a check node starts a new operation, a variable-to-check message (Q) is added t a check-to-variable message (R) obtained in last operation to obtain an APP value updated in the last operation. Then this APP value is deducted from a check-to-variable message (R) obtained by last iteration in this operation to obtain a variable-to-check message (Q). This variable-to-check message is stored back to the memory and put into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored back to the memory to finish the operation of updating the check node and the variable node. Compared to the prior art, this invention has better hardware utilization and less buffer registers, and thus achieves smaller hardware area while remaining the converge speed.