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縮小浮動閘極間距之半導體製程
Patent

縮小浮動閘極間距之半導體製程

台灣積體電路製造股份有限公司, 朱文定, 林崇榮 and 謝佳達
11/11/2003

Abstract

A kind of semiconductor manufacturing process for decreasing the floating gate pitch is disclosed in the present invention. At first, a semiconductor substrate having at least two separation regions is provided, in which a gate dielectric layer is formed between the separation regions. Then, a floating gate, a dielectric layer, a sacrificial layer and a patterned mask layer are sequentially formed on the semiconductor substrate. The patterned mask layer is used as an oxidization mask to perform oxidization treatment onto the sacrificial layer, so as to form plural oxide layers with bird^s beak shape and to remove the patterned mask layer. Then, by using the oxide layers with bird^s beak shape as the etching mask, the non-oxidized sacrificial layer and the dielectric layer are sequentially etched to form an opening that exposes the surface of part of the floating gate layer. After that, the oxide layers with bird^s beak shape are stripped off, and the dielectric layer is used as the etching mask to etch the floating gate along the opening, so as to define the pitch between two floating gates.

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