Abstract
The manufacturing method of single electron transistor structure is obtained by using the manufacture of one-dimensional channel between source and the drain on an SOI chip, and the external bias added to the self-aligned polysilicon on spacer gate to form dual potential energy barrier and quantum dots. In the invention, by conducting electron beam photolithography and directly writing technique onto the multiplayer, the oxidation process characteristic, and the wet etching, a nano-scale one-dimensional channel between the source and the drain is manufactured on the SOI chip, and is etched to form separately located polysilicon spacer gates through the addition of self-aligned manufacture method. A bias is then added to form two potential barriers in the channel and the electron quantum well, which is capable of storing charges and sandwiched between these two potential energy barriers. In addition, the bias control of the metal gate is assisted to obtain the operation of dual-gate single electron transistor structure.