Abstract
The present invention discloses a memory refresh system and operation method thereof. The memory refresh system comprises a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitance of one of a plurality of memory cells of the memory, and generates a corresponding digital code by comparing the voltage and a reference voltage. Each of the memory cells has the corresponding digital code. The combination of the digital codes of the memory cells forms a first state. After a specific period of time, the voltages of the storage capacitances of the memory cells are once detected by comparative detection circuit, and corresponding digital codes are generated and combined to form a second state. The logic circuit compares the first state and the second state for determining whether to change the refresh period or not. Then the timing circuit changes the refresh period according to the result of the determination of the logic circuit.