Abstract
This invention is about built-in self-test (BIST) circuit of memory device. For providing full-speed test, the operation speed of BIST circuit must match the testing speed of memory. Conventionally, a finite state machine is used for the test procedure generated by a set of predefined test evolution. If only using this finite state machine, the bottleneck of function performance will occur. For eliminating this bottleneck, we propose high-speed technique based on prediction logic. By using a prediction logic, certain specific signals of the clock threshold routes can be calculated before a clock cycle. By disposing flip-flop in these signals to break these threshold routes, the clock cycle time is reduced. Our synthetic results indicate that the proposed technique can be used to reduce the clock cycle time up to 30% and a 400 MHz design using 0.35 mu m CMOS cell program base is then introduced.