Abstract
A memory system includes a memory device, a channel and a memory controller device. The memory device includes: a memory array having a read latency, and a write latency that is longer than the read latency; a buffer for two-way data transfer with the memory array; and a transceiver for two-way data transfer with the buffer. The memory controller device is for two-way data transfer with the transceiver through the channel. The memory controller device transmits write data at a write bandwidth for receipt by the transceiver. The transceiver transmits read data at a read bandwidth that is greater than the write bandwidth for receipt by the memory controller device.