Abstract
A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and a read signal during write process and read process. Thereby, the memory is capable of a function of self-timing for write process and read process, and is able to generate a word-line signal with a shorter width in write process to ensure an early start of a precharge timing, thus a whole duty period of the memory can be shortened.